PCIe ASIC Design Engineer
WFA Digital Insight
The demand for skilled ASIC design engineers with expertise in PCIe controller integration has seen significant growth, with the global ASIC market expected to reach $34.4 billion by 2027. Cornelis Networks, a leader in high-performance scale-out networking solutions, is seeking a talented PCIE ASIC Design Engineer to drive the design and integration of PCIe controllers into their next-generation SoCs. With a strong focus on innovation and performance, this role offers a unique opportunity for candidates to work on cutting-edge technology and collaborate with a global team of experts. Before applying, candidates should be prepared to showcase their expertise in PCIE protocol, integration, and silicon bring-up, as well as their ability to work in a fast-paced, dynamic environment.
Job Description
About the Role
Cornelis Networks is a fast-growing company that delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. As a PCIE ASIC Design Engineer, you will play a critical role in the design and integration of PCIe controllers into our next-generation SoCs. You will work closely with cross-functional teams, including architecture, verification, physical design, and software teams, to deliver robust PCIe subsystems. Your expertise in PCIE protocol, integration, and silicon bring-up will be essential in driving the success of our products.The ideal candidate will have a strong background in ASIC/SoC design, with a focus on PCIe controller integration. You will have a deep understanding of high-bandwidth, low-latency connectivity for high-performance compute platforms and be able to collaborate effectively with IP vendors, architecture, verification, physical design, and software teams.
What You Will Do
- Own end-to-end integration of PCIe IP into complex ASIC designs
- Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems
- Drive performance optimization efforts across the PCIe stack, from PHY tuning to DMA/transaction layer efficiency
- Contribute to system architecture and microarchitecture discussions with a focus on IO and interconnect scalability
- Lead silicon bring-up and validation of PCIe links in the lab; work closely with board and firmware teams
- Debug functional and performance issues at RTL, gate-level, and silicon
- Ensure compliance with PCIe specifications and participate in interoperability testing where needed
- Provide mentorship to junior engineers and help define PCIe subsystem development best practices
- Good understanding of high-bandwidth, low-latency connectivity for high-performance compute platforms
What We Are Looking For
- BS/MS in Electrical Engineering, Computer Engineering, or related field
- 10+ years of industry experience in ASIC/SoC design with a focus on PCIe controller integration
- Proven experience in silicon bring-up and debug of complex SoCs
- Strong understanding of PCIE protocol (Gen4/Gen5/Gen6)
- Experience with emulation and post-silicon bring-up
- Good understanding of high-bandwidth, low-latency connectivity for high-performance compute platforms
- Strong analytical and problem-solving skills
Nice to Have
- Experience with system architecture and microarchitecture discussions
- Knowledge of GPU, CPU, and accelerator-based compute clusters
- Familiarity with AI and HPC workloads
Benefits and Perks
- Competitive salary and benefits package
- Opportunity to work on cutting-edge technology with a global team of experts
- Collaborative and dynamic work environment
- Flexible working hours and remote work options
- Professional development opportunities
- Access to the latest tools and technologies
How to Stand Out
- To stand out as a candidate, be prepared to showcase your expertise in PCIE protocol, integration, and silicon bring-up, as well as your ability to work in a fast-paced, dynamic environment.
- Make sure to highlight your experience with emulation and post-silicon bring-up, as well as your understanding of high-bandwidth, low-latency connectivity for high-performance compute platforms.
- Be prepared to provide specific examples of your experience with system architecture and microarchitecture discussions, as well as your knowledge of GPU, CPU, and accelerator-based compute clusters.
- Don't forget to research the company and the role, and be prepared to ask informed questions during the interview process.
- Consider creating a portfolio that showcases your work and accomplishments, and be prepared to discuss your experience and skills in detail.
- Be open to learning and growing with the company, and be willing to take on new challenges and responsibilities.
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