Senior RTL Engineer, Interconnect Design

About the Role

The Senior RTL Engineer will work closely with various teams, including architecture, design, verification, physical design, performance, firmware, and systems engineering, to deliver production-quality silicon for Openai's supercomputing infrastructure. This is a senior, hands-on engineering role that demands broad technical ownership and the ability to drive design from requirements through the full silicon lifecycle.

Openai's commitment to innovation and excellence in AI hardware presents an exciting opportunity for a skilled RTL engineer to make a significant impact. The company's hybrid work model, which includes 3 days in the office per week, offers a balanced approach to work and personal life. Relocation assistance is also available for new employees.

What You Will Do

• Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic.
• Drive third-party engagements to develop novel networking and interface protocols and silicon IP, ensuring high quality and design integrity.
• Perform substantial direct microarchitecture and RTL coding work in Verilog/SystemVerilog.
• Collaborate with architecture and design team members on the overall solution and execution plan for cutting-edge large-scale custom silicon.
• Work with performance and architecture teams to analyze traffic patterns, identify bottlenecks, and optimize interconnect behavior under realistic system workloads.
• Partner with design verification teams to develop verification strategies, coverage plans, assertions, stress scenarios, and debug approaches for highly concurrent fabric behavior.
• Collaborate with physical design teams to ensure interconnect structures are implementable at target frequency, power, and area.
• Provide technical leadership through design reviews, architecture reviews, documentation, mentoring, and development of reusable RTL and integration methodologies.
• Leverage experience to help raise the bar on design work inside the team.
• Plan and oversee the work of junior engineers and help drive productive engineering relationships with external partners.

What We Are Looking For

• Extensive industry experience designing and delivering complex SoC interconnect, NoC, coherent fabric, memory subsystem, cache-coherent, or chip-level integration solutions.
• A strong track record of owning major RTL blocks or SoC subsystems from microarchitecture through tape-out and silicon bring-up.
• Deep expertise in Verilog/SystemVerilog and the development of clean, parameterized, production-quality RTL.
• Strong understanding of interconnect concepts such as topology, routing, arbitration, virtual channels, flow control, buffering, ordering, quality of service, coherency, deadlock avoidance, congestion management, and performance monitoring.
• Experience with common on-chip or chip-to-chip protocols and interfaces, such as AXI, APB, CXL, PCIe, Ethernet.
• Excellent technical leadership skills, with the ability to drive third-party engagements and manage partner execution.
• Strong communication and collaboration skills, with experience working in cross-functional teams.

Nice to Have

• Experience with AI-native silicon development and custom computing at scale.
• Knowledge of emerging interconnect technologies and protocols.
• Familiarity with design verification methodologies and tools.
• Experience with project management and team leadership.

Benefits and Perks

• Opportunity to work on cutting-edge AI-native silicon solutions.
• Collaborative and dynamic work environment with a team of experts in AI hardware.
• Hybrid work model with relocation assistance available.
• Access to state-of-the-art tools and technologies.
• Professional development opportunities, including training and conference sponsorships.
• Competitive compensation package, including equity.
• Comprehensive health insurance and retirement plans.
• Generous PTO and flexible work arrangements.
• Remote stipend and home office setup support.

• Ensure your portfolio showcases your expertise in Verilog/SystemVerilog and interconnect design, with specific examples of complex SoC interconnect projects you've led or contributed to.
• Develop a strong understanding of the current state of AI hardware and the challenges involved in designing scalable on-chip communication fabrics.
• Practice explaining technical concepts, such as interconnect topology and routing, to both technical and non-technical audiences, as strong communication skills are crucial for this role.
• Be prepared to discuss your experience with third-party engagements and how you've managed partner execution in previous roles.
• Consider having a list of questions ready for the interviewer, such as 'What are the biggest challenges facing the SoC design team right now?' or 'How does Openai approach innovation in AI hardware?' to demonstrate your interest in the company and role.
• Review your experience with design verification methodologies and tools, as this will be an important aspect of the job.
• Prepare to discuss your approach to technical leadership and how you've helped raise the bar on design work in previous teams.