Senior Verification Engineer
WFA Digital Insight
As the demand for skilled verification engineers continues to rise, with a projected 25% growth in the next two years, professionals with expertise in SystemVerilog and UVM are in high demand. FortifyIQ, a leader in digital design and verification, stands out for its commitment to innovation and excellence. With the shift towards remote work, this role offers the unique opportunity to work on complex SoC and subsystem designs from anywhere. Candidates should be aware of the importance of strong communication and teamwork skills in this role, as well as the need for analytical and problem-solving mindsets. Before applying, it's essential to understand the current market context, where demand for verification engineers with experience in coverage closure and debugging complex designs is particularly high.
Job Description
About the Role
The Senior Verification Engineer role at FortifyIQ is a critical position that requires a deep understanding of digital design and verification principles. As a senior member of the team, you will be responsible for verifying complex SoC and subsystem designs, ensuring that they meet the required functionality, quality, and coverage goals. This role is ideal for professionals who are passionate about digital design and verification and have a strong background in SystemVerilog and UVM.The day-to-day responsibilities of this role will involve analyzing architectural specifications, defining verification requirements, and developing and maintaining UVM-based verification environments. You will also be working closely with design and architecture teams to align milestones and quality metrics, ensuring that the verification process is efficient and effective.
As a Senior Verification Engineer at FortifyIQ, you will be part of a dynamic team that is dedicated to delivering high-quality digital designs and verification solutions. You will have the opportunity to work on complex and challenging projects, collaborating with experienced professionals who share your passion for digital design and verification.
What You Will Do
- Analyze architectural specifications and define verification requirements
- Develop and maintain UVM-based verification environments
- Create detailed test plans and develop corresponding test cases
- Debug functional issues and contribute to root-cause analysis
- Collaborate closely with design and architecture teams to align milestones and quality metrics
- Develop and maintain scripts and tools to automate verification tasks
- Participate in design reviews and provide feedback on design quality and testability
- Develop and maintain documentation of verification environments and test plans
- Collaborate with other teams to ensure that verification is aligned with overall project goals
What We Are Looking For
- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field
- 7-10+ years of experience in verification or similar roles
- Strong expertise in SystemVerilog and UVM
- Familiarity with Linux and standard EDA tools
- Thorough understanding of the pre-silicon design and verification flow
- Excellent communication, documentation, and teamwork skills
- Experience with coverage closure and debugging complex designs
- Strong analytical and problem-solving mindset
- Ability to work in a fast-paced environment and meet deadlines
Nice to Have
- Experience with scripting languages such as Python or Perl
- Familiarity with Agile development methodologies
- Experience with cloud-based verification platforms
- Knowledge of machine learning or artificial intelligence principles
Benefits and Perks
- Competitive salary and benefits package
- Opportunity to work on complex and challenging projects
- Collaborative and dynamic work environment
- Professional development and training opportunities
- Flexible working hours and remote work options
- Access to cutting-edge technologies and tools
- Recognition and reward for outstanding performance
- Comprehensive health and wellness benefits
- Generous paid time off and holiday package
How to Stand Out
- To stand out as a candidate, highlight your experience with SystemVerilog and UVM, and be prepared to provide examples of your work in these areas.
- Make sure to tailor your resume and cover letter to the specific job requirements, emphasizing your relevant skills and experience.
- Practice your debugging and problem-solving skills, as these are critical components of the verification process.
- Be prepared to discuss your experience with coverage closure and debugging complex designs, and provide specific examples of your work in these areas.
- Don't be afraid to ask questions during the interview process, and be prepared to discuss your career goals and motivations.
- Consider creating a portfolio of your work, including examples of your verification environments and test plans, to demonstrate your skills and experience to potential employers.
- When negotiating salary, be sure to research the market rate for your role and experience level, and be prepared to make a strong case for your value as a candidate.
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