Switch ASIC Design Engineer

About the Role

The role is part of a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. Cornelis Networks values innovation, performance, and scalability, and is committed to solving the world’s most demanding computational challenges with its next-generation networking solutions.

What You Will Do

• Design and implement core components of next-generation Ethernet switch ASICs, focusing on RTL development and latency optimization.
• Develop microarchitecture specifications for high-speed transmit/receive packet processing subsystems.
• Implement RTL designs using Verilog/System Verilog for low-latency data paths, including Network-on-Chip (NoC) and crossbar designs.
• Define timing constraints for RTL blocks and collaborate with Physical Design engineers to optimize timing closure.
• Work with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage.
• Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues.
• Contribute to performance optimization and power-aware design strategies for switch subsystems.
• Collaborate with cross-functional teams to develop and deploy high-performance networking solutions.
• Participate in system-level debug and root cause analysis of technical issues.
• Develop and maintain technical documentation for ASIC designs.

What We Are Looking For

• B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field.
• 10+ years of post-college experience in digital design with proficiency in Verilog and System Verilog.
• Knowledge of Ethernet architecture and networking protocols.
• Prior experience with NoC, crossbar designs, or Ethernet switch ASICs and system debug.
• Experience in RTL design for high-speed or low-latency subsystems in ASICs.
• Familiarity with timing closure and modern physical design methodologies.
• Proven ability in system-level debug and root cause analysis of technical issues.
• Strong verbal and written communication skills.

Nice to Have

• Experience with networking hardware design, particularly in high-performance data analytics and artificial intelligence interconnect solutions.
• Familiarity with TCP/IP, RDMA/RoCE, and IPSec protocols.
• Knowledge of power-aware design strategies and performance optimization techniques.

Benefits and Perks

• Competitive compensation package.
• Opportunity to work on cutting-edge networking solutions for AI and HPC data centers.
• Collaborative and dynamic work environment with a team of experienced professionals.
• Flexible working hours and remote work options.
• Professional development opportunities and training programs.
• Access to the latest tools and technologies in the industry.

• Highlight your experience with Verilog and System Verilog, and be prepared to discuss your understanding of Ethernet architecture and networking protocols.
• Showcase your ability to work on complex ASIC design projects and collaborate with cross-functional teams.
• Emphasize your strong problem-solving skills and experience with system-level debug and root cause analysis.
• Be prepared to discuss your familiarity with timing closure and modern physical design methodologies.
• Research the company and its products to demonstrate your understanding of Cornelis Networks’ mission and values.
• Prepare examples of your previous work, including technical documentation and design specifications, to demonstrate your skills and experience.